Mask structure for manufacture of trench type semiconductor device

ABSTRACT

A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO oxide may be placed between the metal layer and the hard photoresist mask.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/795,026, filed Apr. 26, 2006, the entire disclosure of which isincorporated by reference herein.

FIELD OF THE INVENTION

This invention relates to a process for the manufacture of trench typesemiconductor devices and more specifically relates to a novel maskstructure for such processes.

BACKGROUND OF THE INVENTION

Mask structures are commonly used to control the etching of silicontrenches and for the control of the implantation of impurities into suchstructures. Such mask structures are complex and frequently cannot beused in connection with certain substrate materials, for example,silicon carbide (SiC) which requires long and high temperature processsteps. It would be desirable to have a mask process that can be usedwith SiC substrates, including 4H silicon carbide, as well as othersubstrates such as silicon and the like, in which a single maskstructure can be employed for the trench etch process or for both thetrench etch and implantation process.

BRIEF DESCRIPTION OF THE INVENTION

In accordance with the invention, a mask is formed by a photo resisthard mask atop a thin metal layer (for example, 5000 Å aluminum) whichcovers an oxide layer (1 μm LTO) atop the substrate. Where an SiCsubstrate is used, and a JFET (for example) is to be formed, the trenchneeded may be about 2 μm deep and 1 to 3 μm wide, with adjacent trenchesbeing spaced by mesas about 1.5 to 2.0 μm wide. A photoresist (PR) masklayer is preferably a positive PR and, after development, will permitthe opening of windows and the plasma etch of the exposed underlyingmetal and oxide and the subsequent plasma etch of spaced trenches intothe substrate. The mask can resist the lengthy etch processes and beavailable as a mask to subsequent ion implantation processes.

Thus, the hard mask of the invention can be used for two distinctprocess steps; the trench gate formation (for a JFET) and an ionimplantation doping self-aligned mask.

The hard mask material selection takes into account plasma etchselectivity and ion stopping or blocking range capability, related tothe implant ion species and energy. The mask thickness is adjusted tothe substrate material.

While the invention is applied in the following example to an SiC JFET,the invention is applicable to any trench semiconductor device such asMOSFETs, IGBTs and the like and to other substrate materials than SiC.

Further, it is possible in some applications to eliminate the oxidebuffer layer beneath the metal layer.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a small portion of a starting wafer 10 in cross section. InFIG. 1, the wafer 10 is SiC although other materials could be used.Where the device to be made is a JFET, the starting wafer has an N⁺substrate drain body 11 which may have a thickness of about 350 μm and aconcentration of about 1.8 E 18. An N⁺ buffer layer 12 is atop drainregion 11 and an N type drift region 13 is atop the buffer layer. An N⁺source region 14 is atop the drift layer 13.

The first process step is shown in FIG. 2 and comprises the formation ofoxide 20 (for example, LTO) atop the wafer 10. Oxide 20 may have athickness of about 0.8 μm. An Aluminum layer 21 is then deposited atopoxide 10 to a thickness of about 0.5 μm.

Other options for the layers 20 and 21 which reduce the total maskthickness are, for example, 0.1 to 1.0 μm oxide and 0.1 to 1.0 μm ofaluminum or some other suitable metal.

Note that in some cases, the oxide barrier 20 may be completely removed.

Thereafter, a photoresist (PR) layer 30 (FIG. 3) is formed atop metallayer 21 and is marked and developed as shown, forming spaced etchwindows 40 atop the layer 21.

Photo resist 30 is preferably a positive PR, and is employed in thenovel hard mask structure of the invention for the subsequenttrench/implant steps to be performed.

Thereafter, and as shown in FIG. 4, the metal layer 21 and oxide layerportions exposed by windows 40 are plasma etched to the SiC surface ofwafer.

Finally, as shown in FIG. 5, a dry plasma etch is employed to etchspaced trenches 50 into the SiC drift layer 13.

Photo resist 40 may be removed and the remaining hard mask 20/21 is leftin place for a subsequent ion implant into the trench walls of trenches50.

The trench walls of trenches 50 may be vertical or may form an angle of80° to 90° (vertical) to the wafer surface. That is, the walls of thetrenches may be up to 10° C. to a vertical line through the center ofthe trench and perpendicular to the plane of the wafer.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein.

1. A hard mask for processing a semiconductor wafer comprising a thinmetal layer atop said wafer and a photoresist atop said metal layer. 2.The hard mask of claim 1, which includes an oxide layer between saidmetal layer and said wafer.
 3. The hard mask of claim 1, wherein saidwafer is silicon carbide.
 4. The hard mask of claim 2, wherein saidwafer is silicon carbide.
 5. The hard mask of claim 1, wherein said maskdefines a trench etch for forming a trench in said wafer and an ionimplant for forming an implant into the walls of said trench.
 6. Thehard mask of claim 5, which includes an oxide layer between said metallayer and said wafer.
 7. The hard mask of claim 5, wherein said wafer issilicon carbide.
 8. The hard mask of claim 4, wherein said mask definesa trench etch for forming a trench in said wafer and an ion implant forforming an implant into the walls of said trench.
 9. The hard mask ofclaim 5, wherein the walls of said trench form an angle of 0° to 10° toa vertical line through said trench which is perpendicular to the planeof said wafer.
 10. The mask of claim 1, wherein said thin metal layer isaluminum having a thickness of from about 0.1 μm to about 1 μm.
 11. Themask of claim 2, wherein said oxide layer has a thickness of about 0.1μm to about 10 μm.
 12. The mask of claim 10, wherein said oxide layerhas a thickness of about 0.1 μm to about 1.0 μm.
 13. The hard mask ofclaim 10, wherein said mask defines a trench etch for forming a trenchin said wafer and an ion implant for forming an implant into the wallsof said trench.
 14. The hard mask of claim 11, wherein said mask definesa trench etch for forming a trench in said wafer and an ion implant forforming an implant into the walls of said trench.
 15. The hard mask ofclaim 12, wherein said mask defines a trench etch for forming a trenchin said wafer and an ion implant for forming an implant into the wallsof said trench.
 16. The process of forming a trench in a semiconductorwafer comprising the steps of depositing a thin metal layer atop a topsurface of said wafer; depositing a photoresist atop said metal layer,applying a patterned mask atop said photoresist andphotolithographically developing said photoresist to form a hardphotoresist mask which contains windows corresponding the pattern ofsaid mask, removing the areas of said thin metal layer which are exposedthrough said windows, and forming a trench into the top surface of saidwafer which is exposed by the area removed from said metal layer. 17.The process of claim 16, which includes the step of forming a thin oxidelayer atop said wafer surface and thereafter depositing said thin metallayer atop said thin oxide layer; and removing the areas of said thinoxide layer which are exposed after removal of corresponding areas ofsaid thin metal layer before forming said trench.
 18. The process ofclaim 16, wherein said thin metal layer is aluminum having a thicknessof about 0.1 μm to about 1.0 μm.
 19. The process of claim 17, whereinsaid oxide has a thickness of about 0.1 μm to 1.0 μm.
 20. The process ofclaim 16, which includes the further step of implanting a controlledimpurity into the walls of said trench and masking the surface of saidwafer against the implant by the hard mask comprised of said photoresistand thin metal layer.
 21. The process of claim 17, which includes thefurther step of implanting a controlled impurity into the walls of saidtrench and masking the surface of said wafer against the implant by thehard mask comprised of said photoresist and thin metal layer.
 22. Themask of claim 1, wherein said thin metal layer is selected from thegroup consisting of aluminum, nickel, tungsten and tantalum and has athickness of from about 0.1 μm to about 1.0 μm.
 23. The process of claim16, wherein said thin metal layer is selected from the group consistingof aluminum, nickel, tungsten and tantalum and has a thickness of fromabout 0.1 μm to about 1.0 μm.